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The AEE3298B-K is the perfect FPGA learning kit. You may download your design and test it step-by-step monitoring and/or stimulating over 32 FPGA lines.
The LMS (Logic Monitor / Stimulator) software provides a Logic Analyzer like screen were the user may change and monitor signal and buses states.
You can learn about digital design and verify how it works or even develop a new CPU design and test every function carefully.
All 32KB SRAM pins, on the AEE3298B board, may be accessed from LMS software. Then, you can read or write data on the SRAM while the FPGA is running (assuming the design on the FPGA wont try to access the SRAM at same time) or after disabling the FPGA. With this feature you can write on the SRAM your own instructions for your own CPU design and then make it works, step-by-step or free running.
The figure below is a screen example of the LMS software. As you see the LMS runs in a DOS window. Note the SRAM manual access were the data 0x52 was written and read few steps after. The LMS software is free for download in our LIBRARY page.
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For different installed FPGA include the FPGA code to the Kit code.
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