Designed to work with the AEE3298B FPGA Evaluation Board. Provides access to 32 FPGA lines and all SRAM lines (A0-A15, D0-D7, CS, WR, OE). 32 bit input register tied to 32 bit output register with hardware protection against line contention.

The AEE3499 was designed to work with the AEE3298B board. Its 32 bit I/O lines are tied so you can output one bit and read it to know its real value. If the FPGA or SRAM line is an input you will read the same value you sent out. If the FPGA or SRAM line is an output you will read the actual value of the line, or the value the FPGA or the SRAM did set for this line.

The 32 bit I/O (64 bit data) are updated from the AEE3298B's microcontroller in a serial basis. For it turns, the microcontroller receives new data and send the result from/to the PC computer over the serial interface (19200 bps).

First the microcontroller places the new 32 bit data over the 32 FPGA lines. Four microseconds later it reads the 32 bit inputs and sends back to the computer where the LMS (Logic Monitor / Stimulator) software shows on the computer's screen.