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The compression method used in the AEE FPGA products use a proprietary algorithm designed to handle FPGA configuration files. It is a two step data analysis with progressive compression where one bit can represents a full byte. The algorithm development focused in a simple decompression software implementation so it can easily run in very small microcontrollers. The compression rate is affected
by the design density. The best results are achieved when the
design uses less resources of the target FPGA so the configuration
file contains more 0xFF (or 0x00 for the VIRTEX) bytes. At first sight the compression rate isn't impressive. However, the algorithm cannot loose even a single bit and it needs to be easy to implement in a simple microcontroller program. When using the WinZip utility in the examples above they were compressed to 5940 bytes (50%) and 4338 bytes (64%) respectively. Not much better since it uses a high complexity software, large memory and a big CPU. Also, the decompression algorithm
allows a quick configuration since the microcontroller may generate
many bytes of configuration for each byte it needs to read from
the memory. The advantages of the compression technique are:
Contact AEE to know how you could use this technique in your products. |