Product: AEE3599 - Xilinx FPGA Configuration Device Forecast date to release: December, 1999 Introductory price: < $12.00 in +100 units The AEE3599 is a low cost chip designed to configure FPGAs using a serial EEPROM and a serial communication channel to get configuration data from the host. The AEE3599 is compatible with EEPROM size of 32 or 64K bytes (24LC256 or 24LC512) and capable of addressing up to 8 memory chips. It may hold several configuration files for one FPGA or merged files to configure a chain of FPGAs. The configuration files are stored using a proprietary compression algorithm that results in up to 60% reduction of the original size. It allows to handle from 400K bits (one 24LC256) to 6.7M bits (eight 24LC512) of configuration length. A special feature enables safe download mode. In this mode the device may receive and store a new configuration file while the old one remains protected in the EEPROM. When the new file is fully stored and verified the old one is erased and the FPGA reconfigured with the new file. The device set the EEPROM to low power operation and enters itself in Power-Down mode after the FPGA configuration. The wake-up occurs when the FPGA looses the configuration or in a presence of serial communication request. The power supply is 2.5 to 5V and consumption is less than 2 uA in Power-Down mode. An internal 4MHz clock oscillator reduces the system cost. Devices for external crystal use may be ordered and allows running at up to 20MHz.

Product: LMSW (LMS for Windows) - Logic Monitor / Stimulator software Forecast date to release: January, 2000 Introductory price: FREE The LMSW, or LMS for Windows, runs in the same way of the LMS for DOS. Some new features are provided from the Windows environment like object handling and printing. Also, it will execute a script enabling step counter for free-running, signal or bus state verifying and behavior changing, clock genaration, logic tests and conditional stop. With script execution the LMSW allows automated verify of a large design behavior (such as a CPU design with execution of every instruction).